The DLX is a RISC processor architecture design by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store architecture. Intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses. This purpose is quite similar to Donald Knuth's MIX and MMIX architectures, from The Art of Computer Programming.
In the original MIPS design one of the methods used to gain performance was to force all instructions to complete in one cycle, forcing the compiler to insert "no-ops" in cases where the instruction would definitely take longer, as in memory access for instance. In the DLX design a more modern approach to long instructions was used, using a data-forwarding system and reordering instructions. In this case the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they do complete. Externally it appears execution occurred linearly.
DLX instructions can be broken down into three types, R-type, I-type and J-type. R-type instructions are pure register instructions, with three register references contained in the 32-bit word. I-type instructions specify two registers, and use 16 bits to hold an immediate value. Finally J-type instructions are jumps, containing a 26-bit address.
